1. Field of the Invention
The present invention relates to an integrated circuit having at least one electrical conductor boosted to a voltage in excess of a power supply voltage.
2. Description of the Prior Art
The use of voltages in excess of the power supply voltage is common in integrated circuits, especially those implemented in field effect transistor (FET) technology. The "boosted node" technique is used typically to overcome the threshold voltage drop (Vth) of a FET when it is desired to pass a signal therethrough (i.e., from source to drain) without reducing the magnitude of the signal. For example, in dynamic random access memory (DRAM) design, the use of a boosted row conductor is typical. This technique increases the gate voltage on the access transistors in a selected row so that the threshold voltage drop does not substantially reduce the voltage level of the data stored in the respective storage capacitors. Other boosted node applications include boosting a clock or logic signal applied to transmission gate FET's, for performing delay and logic functions.
A typical prior art circuit for obtaining a boosted voltage is shown in FIG. 1, with others being known in the art. An input signal, for example a clock signal, is applied to input node 100. The voltage of the input signal assumes either a high or low level at a given time. These levels may be the values of the positive and negative power supply voltages supplied to the integrated circuit (for example, 0 and 5 volts), or other values sufficient to switch M11 between conducting and nonconducting states. When in the low voltage state (0 volts) the inverter 101 places a high voltage level on the gate of transistor M10, allowing it to conduct. Hence, the output node 102 is placed at the level of Vss, the negative supply voltage (0 volts). When the input signal goes to a high level (5 volts), inverter 101 turns transistor M10 off. Also, transistor M11 is turned on, so that positive power supply voltage, Vcc, minus the threshold voltage drop of M11, initially appears at output node 102. If Vth for M11 is 1.5 volts, for example, then 5-1.5=3.5 volts initially appears at node 102.
The boost capacitor 106 is also charged at this time, since the 3.5 volt signal appears on the plate connected to node 102, and a low voltage, about 0 volts, initially is present on the opposite plate, at node 105. The node 105 remains at this low voltage state until the above-noted high voltage (3.5 volts) from node 102 is propagated through inverter 103, 104. This short delay time allows the charging of the boost capacitor. When the high voltage state propagates from node 102 through the inverters 103, 104, the capacitor plate at node 105 is placed at a high (e.g., 5 volt) level by inverter 104. The voltage on the opposite plate (at node 102) is "boosted" from 3.5 volts to a higher voltage level. The maximum boost value will be determined in part by the load connected to node 102. For example, a load capacitance C.sub.LOAD reduces the boost by dividing the voltage available from boost capacitor 106. When the input signal returns to a low level, the output node 102 is also returned to a low level, by conduction through M10 as above. The boosted voltage at node 102 may also decay to a lower value than the maximum boost value due to leakage currents even before this time.
One problem with prior art boost generators has become more apparent as the gate oxides of devices connected to the boosted node are decreased. Then, the electric fields increase across such devices if the boost voltage is maintained at a given value. For example, the gate oxides of DRAM access transistors are subjected to excessive electrical stress if subjected to the high fields produced by prior art techniques over prolonged periods of time. This can lead to failure of a device, or degradation of its performance. Therefore, means have been included in boost generators to limit the amount of boost they produce. For example, diode 107 in FIG. 1 has been added to prevent the boosted voltage on output node 102 from exceeding the positive power supply voltage level by more than one diode voltage drop. This limits the boost to about Vcc+0.6 volts in the case of a slilcon diode. A typical graph showing the boosted voltage versus Vcc for the case of diode limiting is shown in FIG. 2 for the exemplary circuit of FIG. 1. Other voltage limiting means, for example a diode-connected FET, are also possible for achieving similar results.